There's a wrinkle, and it's that each of the 256 destinations is organized to hold four bytes, not two. This is evident on the schematic. The Jump Destination Register drives eight EPROM address inputs, the lowest of these being A2. But A1 of the EPROM is driven by Phase Two, and A0 is driven by the so-called Flag Bit (which contains the result of the Input Test that occurs on every instruction). When the Flag Bit is true, "true" instruction bytes will be fetched (ie; with EPROM A0 =1). When the Flag Bit is false, EPROM A0 will =0 and "false" instruction bytes will be fetched.
That is the basis of the two-way branch mentioned earlier. The Input Test during Phase One selects one of the eight inputs to the 4051 mux, and that input's value is clocked into the Flag Bit at the start of Phase Two. During Phase Two, the Jump Destination is fetched, and the fetch will occur either with EPROM A0 =1 or =0, depending on the state of the 4051 input that was tested. Thus two different jump destinations can result.
The machine always jumps from one instruction to the next. It doesn't know how to "fall through" to the "next" address because it has no program counter and no ability to count (compute an increment). Thus there's no advantage to structuring conditional branches in the usual way; ie, "branch, else fall through to the instruction at address+1." If you have a program counter then Address+1 is useful as an implicit default — it lets you shrink the instruction size. But nothing is implict with this machine; there's always an explicit jump address for both outcomes of the condition test.
That said, instructions do tend to get stored in sequential order, and conditional branches very often do specify address+1 as one of the outcomes. That's the way a human writes source code, and of course the assembler doesn't care.
As mentioned, every instruction includes both an Input/branch operation and an
Output operation. But that will rarely match
the needs of the program! The programmer needs
the freedom to specify several Input/branch operations in a row, for
example, or
several Output operations in a row. The problem is resolved by
providing a means within each instruction
to neutralize whichever operation is unwanted.
An unwanted Input/branch operation is neutralized simply by making both branch destinations the same. It doesn't matter which input you specify for testing, since the test result is ignored. Only the Output portion of the instruction will have any meaningful effect.
As for neutralizing an Output operation, one bit (Q7) of the 4099 addressable latch is left unconnected for this exact purpose. It is reserved as a Write-Only-Memory! In other words, when you want the Output operation to be a NOP, code it to write to Q7. It doesn't matter whether you write a 1 or a 0. Q7 goes nowhere, leaving only the Input/branch portion of the instruction with any meaningful effect.
This computer has no RAM
as such, making it awkward if you
need to
store a bit of
information. One approach is to simply branch the program into two
paths, based on the status of the bit you need to remember.
But, for long-term storage, a better approach is to write the bit to
one of the dedicated 4099 outputs which connect back to 4051
inputs. This allows the stored information to be read back when needed.
(The schematic shows two such I/O-mapped
memory bits.)
In the printing press application, one of the memory bits is used to guide subroutine returns. There are two main parts to the program, and they share a few subroutines. At the exit of each subroutine, a memory bit (previously prepared by the caller) is tested to see which of two return addresses to jump to.
Also notable on the schematic are an RC filter to de-glitch the input line, and a Reset circuit that forces the EPROM to select a shadow array filled entirely with unconditional "Jump to Start" instructions.
The clock oscillator can easily be replaced by a square wave derived from the AC power line. Of course this computer is capable of running a lot faster than 60 Hz, but 60 Hz is plenty fast enough for this application. I chose the low operating frequency merely because it simplified implementation of a software time delay.
Two sections are unused on the lower 74C374 register. This means a 74C174 could replace the '374, reducing space requirements. Alternatively, one of the 374's unused sections could capture the unused bit from the EPROM, providing an extra address line to double the machine's Input or Output space via an additional 4051 or 4099.